The present invention relates to a method for fabricating a highly integrated semiconductor apparatus, and more particularly, to a method for fabricating a semiconductor device having a buried word line structure capable of stably operating in a highly integrated semiconductor memory apparatus.
In general, a semiconductor memory apparatus includes a plurality of unit cells each of which consists of a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transmit data between a bit line and the capacitor in response to a control signal, e.g., a voltage level of a word line, using a property of semiconductor whose electrical conductivity changes depending on the environment. The transistor includes three regions of a gate, a source and a drain, and charge movement between the source and the drain occurs depending on the control signal inputted to the gate. The charge movement between the source and the drain is performed through a channel region.
In case of forming a typical transistor using a semiconductor substrate, a gate is formed on the semiconductor substrate, and a source and a drain are formed by doping impurities into portions of the semiconductor substrate at both sides of the gate. However, as the data storage capacity and a degree of integration of a semiconductor memory apparatus increase, a size of each unit cell is being required to be smaller. That is, the design rule of a capacitor and a transistor included in the unit cell has been reduced, and thus a channel length of the cell transistor has been gradually decreased. As a result, a short channel effect and drain induced barrier lower (DIBL) have occurred in the typical transistor, which deteriorated the operational reliability of the transistor. The above drawbacks occurring as a result of the reduction of the channel length can be overcome by maintaining a threshold voltage to allow the cell transistor to perform a normal operation. In general, as the channel length of the transistor has been smaller, the doping concentration of impurities in a region where a channel is formed has been increased.
However, as the design rule goes less than 100 nm, the doping concentration in the channel region is further increased as much as the extent to which the reduction of the design rule increases an electric field in a storage node (SN) junction. As a result, it may cause another drawback that a refresh property of the semiconductor memory apparatus is deteriorated. To overcome this drawback, a cell transistor having a three-dimensional channel structure is employed to maintain a channel length thereof although the design rule is reduced. In such a three-dimensional channel structure, a long channel is formed in a vertical direction. Namely, since the channel length is secured in the vertical direction although a channel width is small in a horizontal direction, the doping concentration may be reduced, and thus the deterioration of the refresh property may be minimized.
Meanwhile, as the degree of integration of the semiconductor memory apparatus is getting higher, a distance between a bit line and a word line that are coupled to the cell transistor becomes smaller. As a result, parasitic capacitance generated between the bit line and the word line increases, and the increasing parasitic capacitance deteriorates an operational margin of a sense amplifier amplifying data transmitted through the bit line. This is fatal to the operational reliability of the semiconductor memory apparatus. In order to solve the above drawbacks, a buried word line structure has been introduced to reduce the parasitic capacitance between the bit line and the word line. In the buried word line structure, the word line is formed only in a recess and not exposed over the surface of the semiconductor substrate. That is, the word line is buried in the semiconductor substrate by forming a conductive material in the lower part of a recess formed in the semiconductor substrate and covering the upper part of the recess with an insulation layer. As a result, the word line can be electrically isolated from the bit line formed on the semiconductor substrate in which source/drain is formed.
FIG. 1 is a cross-sectional view illustrating a semiconductor device having a buried gate in a typical semiconductor apparatus.
Referring to FIG. 1, an isolation layer 104 defining an active region is formed in a semiconductor substrate 102 through a shallow trench isolation (STI) method. After forming an insulation layer 106 on the active region and the isolation layer 104, a recess (not shown) for forming a gate pattern is formed through an exposure process. Subsequently, a buried gate 108 is formed by filling a lower portion of the recess with conductive material, and a nitride layer 110 is deposited in an upper portion. Then, although it is not shown, a bit line contact is formed to be coupled between two neighboring buried gates 108 formed in the active region by patterning the nitride layer 110, and a storage node contact is formed between the buried gate 108 and the isolation layer 104.
Particularly looking at a process of forming the buried gate 108, after depositing the conductive material on the semiconductor substrate 102 including the recess, the conductive material is planarized until the top surface of the insulation layer 106 is exposed by performing a chemical mechanical polishing (CMP) process. After then, an etch-back process is performed using the difference between an etch rate of the insulation layer 106 and that of the conductive material so that the conductive material remains in the lower portion of the recess. As a result, the buried gate 108 is formed. Subsequently, the nitride layer 110 is deposited on the buried gate 108.
The semiconductor device fabricated through the above processes has problems caused by a property of the etch-back process that is performed to form the buried gate 108 described in FIG. 1. That is, the conductive material filled in the upper portion of the recess is not fully planarized but remains on a sidewall of the recess, so that the conductive material can be removed only at the center of the recess as much as the etch depth. In the case that the semiconductor device is fabricated with allowing the conductive material to remain on the sidewall of the recess, if a voltage is supplied to the word line, an electric field may be concentrated on the conductive material remaining on the sidewall of the recess. Therefore, when using such a semiconductor device as a cell transistor, an operational property of a unit cell may be deteriorated by the electric field, and a data storage time may be also shortened by a leakage current generated by the electric field.
Moreover, if the conductive material is not completely removed from the sidewall of the recess, a problem may occur that a bit line contact formed in a subsequent step is electrically coupled with the conductive material. This phenomenon may occur in a process of forming a storage node contact and the bit line contact as well. The junction failure that the buried gate 108, i.e., the word line, is electrically coupled with the bit line contact or the storage node contact may deteriorate the operational reliability of a semiconductor device.